Mask/Reticle Defects
To fabricate an integrated circuit (IC) in a semiconductor substrate, a physical representation of the IC is transferred onto a pattern tool. Then, the pattern tool is exposed to transfer this pattern onto the semiconductor substrate. A mask is a standard pattern tool used in IC processing. Typically, a mask includes patterns that can be transferred to the entire semiconductor substrate (for example, a wafer) in a single exposure. A reticle, another standard pattern tool, must be stepped and repeated to expose the entire substrate surface. For ease of reference herein, the term “mask” refers to either a reticle or a mask.
A typical mask is formed from a quartz plate having a chrome coating. Generally, a mask is created for each layer of the IC design. Specifically, a portion of the IC layout data file representing a physical layer (such as a polysilicon layer or a metal layer) is etched into the chrome layer. Thus, each mask includes the pattern that represents the desired circuit layout for its corresponding layer. In high density ICs, a mask can also include optical proximity correction (OPC) features, such as serifs, hammerheads, bias, and assist bars. These OPC features are sub-resolution features used to compensate for process artifacts and/or proximity effects.
In high-density IC designs, those skilled in the art of IC fabrication have recognized the importance of using masks that provide accurate representations of the original design layout. Unfortunately, a “perfect” mask is not commercially viable. In fact, even under optimal manufacturing conditions, some mask defects can occur outside the controlled process.
A defect on a mask is any deviation from the design database (i.e. an irregularity) that is deemed unacceptable by an inspection tool or an inspection engineer. FIG. 1 illustrates a flowchart 100 of a prior art method of inspecting an integrated circuit. In step 110, an IC is designed. In step 112, a data file of mask design data, e.g. a layout of the IC, is created. This data is used to manufacture the mask in step 114. At this point, the mask is inspected in step 116 by scanning the surface of the mask with a high-resolution microscope and capturing images of the mask. Irregularities in the mask are identified in a list by their location. In one embodiment, the mask has an associated grid pattern and the list designates the squares in the grid pattern in which the irregularities are located. This inspection and irregularity identification can be performed by specialized equipment/software provided by companies such as KLA-Tencor or Applied Materials.
To determine whether the mask passes inspection (step 118), a skilled inspection engineer or a semi-automated inspection device reviews the irregularities identified in step 116. Note that only irregularities deemed to be outside the tolerances set by the manufacturer or user are characterized as defects. If irregularities are discovered and are outside tolerances, then a determination is made in step 128 if the mask can be repaired. If the mask can be repaired, then the mask is cleaned and/or repaired in step 130 and the process returns to step 116 of inspecting the mask. If the mask cannot be repaired, then a new mask must be manufactured and the inspection process returns to step 114. If the mask passes inspection, as determined in step 118, then an actual wafer is exposed using the mask in step 120.
To ensure that the mask has produced the desired image on the wafer, the wafer itself is typically inspected in step 122. If irregularities are discovered and are outside tolerances as determined in inspection step 124, then a determination is made in step 128 if the mask can be repaired. If the mask can be repaired, then the mask is cleaned and/or repaired in step 130 and the process returns to step 116 of inspecting the mask. If the mask cannot be repaired, then a new mask must be manufactured and the inspection process returns to step 114. If irregularities on the wafer are discovered, but are determined to be within tolerances, then the mask passes inspection in step 124 and the inspection process ends in step 126.
Unfortunately, the above-described process has a number of significant disadvantages. For example, an automated inspection device measures tolerance principally by size. Thus, if a pinhole on the mask has a predetermined size, then the automated inspection device would probably designate the pinhole as a defect regardless of its location on the mask. In contrast, a skilled inspection engineer can use additional, more subjective methods based on his/her level of experience. Specifically, an experienced engineer might be able to determine whether a pinhole of even less than the predetermined size but in a critical area would have an adverse effect on functionality or performance and therefore should be characterized a defect, or whether a pinhole greater than the predetermined size but not in a critical area would not affect functionality or performance. However, this skill set must be developed over time at considerable expense. Moreover, like all human activity, even after developing this skill set, the quality of review inevitably varies. Thus, the step of characterizing the irregularity is prone to error.
Another disadvantage of the above-described process is the triggering of false defect detections. For example, an automated inspection device can falsely report an OPC or an imperfect OPC feature as a defect. As noted previously, an OPC feature is a sub-resolution feature used to compensate for proximity effects. Therefore, the OPC feature would typically not constitute nor contribute to a defect.
Mask Inspection System
To address these disadvantages, a mask inspection system designed by Numerical Technologies, Inc. provides mask quality assessment without resorting to an actual exposure of a wafer. This mask inspection system is described in U.S. patent application Ser. No. 09/130,996 (herein referenced as the NTI system), entitled, “Visual Inspection and Verification System”, which was filed on Aug. 7, 1998 and is incorporated by reference herein.
FIG. 2 illustrates a process 200 of inspecting a mask for defects in accordance with the NTI system. Process 200 utilizes an inspection tool 202 and a wafer image generator 209. In one embodiment, inspection tool 202 includes an image acquirer 203, typically a high resolution imaging device, to scan all or a portion of a physical mask 201. A defect detection processor 204 compares the mask images provided by image acquirer 203 to a set of potential defect criteria and determines what areas of the mask contain potential defects. If a potential defect is identified, defect detection processor 204 signals a defect area image generator 205 to provide a defect area image of the area including and surrounding the potential defect.
In one embodiment, inspection tool 202 then provides defect area image data 206 to wafer image generator 209. In another embodiment, this data is digitized by digitizing device 207, stored in storage device 208, and then provided to wafer image generator 209 at a later point in time. In yet another embodiment that analyzes both areas identified as potential defects and areas not identified as potential defects, the scanned image provided by image acquirer 203 can be provided directly to wafer image generator 209 or indirectly through digitizing device 207 and storage device 208.
Wafer image generator 209 includes an input device 210 that receives data directly from inspection tool 202 in a real time feed or off-line data from storage device 208. An image simulator 211 receives the information from input device 210 as well as other input data, such as lithography conditions 212. Lithography conditions 212 can include, but are not limited to, the wavelength of illumination, the numerical aperture, the coherence value, the defocus (wherein the term defocus as used herein refers to focal plane positioning), the exposure level, lens aberrations, substrate conditions, and the required critical dimension. Using these inputs, image simulator 211 can generate a wafer image 213 that simulates physical mask 201 being exposed on a wafer. Image simulator 211 can also generate a simulated process window 214, and performance output 215. In one embodiment, image simulator 211 also takes into account the photoresist and/or the etching process as indicated by block 216.
Although process 200 provides valuable information to the customer via the simulated wafer image 213, for example, the customer must still review that information to make a determination regarding the appropriate action to take (e.g. repair the mask or fabricate a new mask). Thus, process 200 can be subject to human error. Therefore, a need arises for a mask inspection system and process that provides an objective, accurate measure of mask defect printability and mask quality.